Draft:OpenHW Foundation
Review waiting, please be patient.
This may take 2 months or more, since drafts are reviewed in no specific order. There are 1,692 pending submissions waiting for review.
Where to get help
How to improve a draft
You can also browse Wikipedia:Featured articles and Wikipedia:Good articles to find examples of Wikipedia's best writing on topics similar to your proposed article. Improving your odds of a speedy review To improve your odds of a faster review, tag your draft with relevant WikiProject tags using the button below. This will let reviewers know a new draft has been submitted in their area of interest. For instance, if you wrote about a female astronomer, you would want to add the Biography, Astronomy, and Women scientists tags. Editor resources
Reviewer tools
|
Comment: In accordance with the Wikimedia Foundation's Terms of Use, I disclose that I have been paid by my employer for my contributions to this article. CharlesLMS (talk) 12:35, 2 July 2026 (UTC)
| Type | NPO |
|---|---|
| Purpose | Accelerate development and adoption of open source RISC-V processor cores and related IP |
| Members | 30+ members |
| Website | openhwfoundation |
The OpenHW Foundation (formerly OpenHW Group) is an international non-profit organization that develops open source processor cores and related hardware IP artefacts based on the RISC-V instruction set architecture. Founded in 2019, the organization coordinates collaborative development of production-grade open semiconductor hardware among semiconductor companies, research institutions, and universities. Since 2025, it has operated as an Eclipse Foundation working group.
History
The OpenHW Group was founded in June 2019[1] . According to EE Times, the organization was established to address the gap between academic RISC-V research and commercially deployable processor intellectual property by producing industrial-grade open source processor cores[2].
In 2023 Florian Wohlrab succeeded founder Rick O'Connor as chief executive officer[3].
In October 2025, the OpenHW Group announced that it would join the Eclipse Foundation, where it was re-established as the OpenHW Foundation[4][5][6][7].
Organization
The foundation operates under the Eclipse Foundation's vendor-neutral governance model. Technical activities are overseen by a Technical Steering Committee composed of representatives from member organizations.
Projects
The foundation's primary technical activity is development of the CORE-V family of RISC-V processor cores together with associated verification environments and interface specifications:
- CVA6, a 64-bit application processor derived from ETH Zürich's Ariane processor
- CV32E40P, a 32-bit embedded processor originating from the PULP Platform
- CV32E40S and CV32E40X, embedded processor cores targeting safety and extensibility
- CVE2, a family of compact embedded processors derived from lowRISC's Ibex processor
- CV-Wally, an 64bit application ready processor from Harvey Mudd Collage
- CORE-ET, an open source edge AI fabric IP leveraging RISC-V Cores
- CORE-V-VERIF, an open verification environment for CORE-V processors
- CV-X-IF, an interface specification for integrating custom accelerators with RISC-V processors
- OBI, an interface protocol used for point-to-point interfaces to instruction and data memories in embedded systems
The foundation also contributes to collaborative European semiconductor initiatives, including the Chips Joint Undertaking project TRISTAN[8] and hosts the Unified RISC-V IP Access Platform[9].
Industry adoption
The OpenHW Foundation's processor cores have been incorporated into multiple hardware and software platforms.
In 2022 the organization introduced the CORE-V MCU Development Kit, an open-source microcontroller platform intended to simplify development and evaluation of RISC-V systems[10].
In 2023 the foundation announced the CORE-V CVA6 Platform Project, intended to provide a complete software and hardware platform around the CVA6 processor[11].
In 2026, Thales demonstrated a performance model of the OpenHW Foundation CVA6 RISC-V processor to evaluate performance-related modifications before implementing them in RTL[12][13].
In 2026 the Eclipse Foundation announced that the ThreadX v6.5.1 release, made available in June 2026, added support for the CVA6 core and the CORE-V MCU. The project team stated its intent to work on CV-Wally support in the future[14].
See also
References
- ^ "OpenHW Group Launched". HPCwire. Retrieved 2026-07-02.
- ^ Dahad, Nitin (2019-06-14). "RISC-V Moving Beyond Academia, New Group offers Hardened SoCs". EE Times. Retrieved 2026-07-02.
- ^ "OpenHW Group Appoints Florian 'Flo' Wohlrab as New CEO to Spearhead Open-Source Ecosystem Advancement". Archived from the original on 2026-05-10. Retrieved 2026-07-02.
- ^ "Eclipse Foundation Announces New Open-Source Collaborations and Working Groups with Focus on Regulatory Compliance". ARC Advisory Group. 2024-10-08. Retrieved 2026-07-02.
- ^ "L'OpenHW Group rejoint la fondation Eclipse - L'INFORMATICIEN & L'INFO CYBER-RISQUES - L'1FO Tech par L'Informaticien - L'INFORMATICIEN - L'1FO Tech par L'Informaticien". www.linformaticien.com. Retrieved 2026-07-02.
- ^ Bantle, Ulrich (2024-10-09). "Risc-V-Entwicklung: OpenHW tritt Eclipse Foundation bei". Linux-Magazin (in German). Retrieved 2026-07-02.
- ^ Desbiens, Frédéric (2025-06-05). "En god strategi for mikrokontroller-utvikling". elektronikknett (in Norwegian Bokmål). Retrieved 2026-07-02.
- ^ "Team". TRISTAN. Retrieved 2026-07-02.
- ^ "Introducing the European Unified RISC-V IP Access Platform (UAP)". HiPEAC. 2026-02-23. Retrieved 2026-07-02.
- ^ "OpenHW Group Opens Orders for the Open-Hardware CORE-V MCU DevKit, Boasting a Free RISC-V SoC Design". Hackster.io. Retrieved 2026-07-02.
- ^ Media, OpenSystems. "New CORE-V CVA6 Platform Project Announced at RISC-V Summit". Embedded Computing Design. Retrieved 2026-07-02.
- ^ Staff, RISC-V. International (2026-03-24). "Using a Performance Model to Implement a Superscalar CVA6". RISC-V International. Retrieved 2026-07-02.
- ^ Tedeschi, Riccardo; Ottavi, Gianmarco; Allart, Côme; Wistoff, Nils; Fu, Zexin; Grillotti, Filippo; Ambroggi, Fabio De; Guidetti, Elio; Rigaud, Jean-Baptiste (2025-05-08). "CVA6S+: A Superscalar RISC-V Core with High-Throughput Memory Architecture". arXiv:2505.03762 [cs.AR].
- ^ Gentry, Ally (2026-04-27). "Eclipse ThreadX and RISC-V Advance the Open Embedded Stack". Efficiently Connected. Retrieved 2026-07-02.
Category:RISC-V Category:Open source Category:Semiconductor IP cores
Content Disclaimer
Informasi ini disarikan dari Wikipedia dan disajikan kembali untuk tujuan edukasi. Konten tersedia di bawah lisensi CC BY-SA 3.0. Kami tidak bertanggung jawab atas ketidakakuratan data yang bersumber dari kontribusi publik tersebut.
- The information displayed on this website is sourced in part or in whole from Wikipedia and has been adapted for the purpose of restating it. We strive to provide accurate and relevant information, however:
- There is no guarantee of absolute accuracy. Wikipedia is an open, collaborative project that can be edited by anyone, so information is subject to change.
- It is not intended to constitute professional advice. The content displayed is for informational and educational purposes only. For important decisions (e.g., medical, legal, or financial), please consult a professional.
- Content copyright. Wikipedia is licensed under the Creative Commons Attribution-ShareAlike License (CC BY-SA). This means that content may be reused with appropriate attribution and shared under a similar license.
- Responsible use. Any risk arising from the use of information from this website is entirely the responsibility of the user.
