Machine Check Architecture
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In computing, Machine Check Architecture (MCA) is an Intel and AMD mechanism in which the CPU reports hardware errors to the operating system.
Machine check architecture was introduced by Intel with the P6 family and has been implemented in all subsequent Intel processor families, including the Core, Xeon, and current generations, as well as the (now discontinued) Itanium architecture.[1] AMD has implemented the architecture since its K7 family, continuing through the K8 and current Zen-based processor families.[2] The architecture provides a mechanism for detecting and reporting hardware (machine) errors, such as: system bus errors, ECC errors, parity errors, cache errors, and translation lookaside buffer errors.[1] It consists of a set of model-specific registers (MSRs) that are used to set up machine checking and additional banks of MSRs used for recording detected errors, with the number of available banks having increased substantially in modern multi-core and multi-die processor designs to isolate errors by component.[1]
See also
- High availability (HA)
- Machine-check exception (MCE)
- Reliability, availability and serviceability (RAS)
- Windows Hardware Error Architecture (WHEA)
References
- ^ a b c Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide, Part 2. Intel Corporation. September 2023. p. 16-1. Retrieved September 19, 2025.
- ^ "BIOS and Kernel Developer's Guide (BKDG) for AMD Family 17h Models". AMD.
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External links
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