This article contains information about Intel's GPUs (see Intel Graphics Technology) and motherboard graphics chipsets in table form. In 1982, Intel licensed the NEC μPD7220 and announced it as the Intel 82720 Graphics Display Controller.[1][2]
6.0 (full) 9.0 (some features, no hardware shaders)
Second generation
Intel marketed its second generation using the brand Extreme Graphics. These chips added support for texture combiners allowing support for OpenGL 1.3.
Each EU contains 2 × 128-bit FPUs and has double peak performance per clock cycle compared to previous generation. One supports FP32 and FP64, and the other supports only FP32. Since the throughput of FP64 instructions are 2 cycles, the FP64 FLOPS is a quarter of the FP32 FLOPS. Only one of the FPUs supports 32-bit integer instructions.
Each Subslice contains 6 or 8 (or 10 in Haswell GPUs) EUs and a sampler, and has 64 KB shared memory.
Each EU contains 2 × 128-bit FPUs and has double peak performance per clock cycle compared to previous generation. One supports FP32 and FP64, and the other supports only FP32. Since the throughput of FP64 instructions are 2 cycles, the FP64 FLOPS is a quarter of the FP32 FLOPS. Only one of the FPUs supports 32-bit integer instructions.
Each Subslice contains 6 or 8 (or 10 in Haswell GPUs) EUs and a sampler, and has 64 KB shared memory.
Each EU contains 2 x 128-bit FPUs. One supports 32-bit and 64-bit integer, FP16, FP32, FP64, and transcendental math functions, and the other supports only 32-bit and 64-bit integer, FP16 and FP32. Thus the FP16 (or 16-bit integer) FLOPS is twice the FP32 (or 32-bit integer) FLOPS. Since the throughput of FP64 instructions is one per 2 cycles, the FP64 FLOPS is a quarter of the FP32 FLOPS.
Each Subslice contains 8 EUs and a sampler (4 tex/clk[47]), and has 64 KB shared memory.
For Windows 10, the total system memory that is available for graphics use is half the system memory. For Windows 8, it is up to 3840 MB. On Windows 7, it is up to about 1.7 GB through DVMT.
Specifications of Intel HD Graphics series[48][49]
Each EU contains 2 x 128-bit FPUs. One supports 32-bit and 64-bit integer, FP16, FP32, FP64, and transcendental math functions, and the other supports only 32-bit and 64-bit integer, FP16 and FP32. Thus the FP16 (or 16-bit integer) FLOPS is twice the FP32 (or 32-bit integer) FLOPS. Since the throughput of FP64 instructions are 2 cycles, the FP64 FLOPS is a quarter (eighth in Apollo Lake) of the FP32 FLOPS.
Each Subslice contains 8 EUs (two of which are disabled in GT1) and a sampler (4 tex/clk), and has 64 KB shared memory.
For Windows 10, the total system memory that is available for graphics use is half the system memory. For Windows 8, it is up to 3840 MB. On Windows 7, it is up to about 1.7 GB through DVMT.
Each EU contains 2 x 128-bit FPUs. One supports 32-bit and 64-bit integer, FP16, FP32, FP64, and transcendental math functions, and the other supports only 32-bit and 64-bit integer, FP16 and FP32. Thus the FP16 (or 16-bit integer) FLOPS is twice the FP32 (or 32-bit integer) FLOPS. Since the throughput of FP64 instructions are 2 cycles, the FP64 FLOPS is a quarter of the FP32 FLOPS.
Each Subslice contains 8 EUs and a sampler (4 tex/clk), and has 64 KB shared memory.
^ shading cores (ALU):texture mapping units (TMU):render output units (ROP):ray tracing units:tensor cores (XMX):execution Units
^ Boost values (if available) are stated below the base value in italic.
^ Pixel fillrate is calculated as the lowest of three numbers: number of ROPs multiplied by the base core clock speed, number of rasterizers multiplied by the number of fragments they can generate per rasterizer multiplied by the base core clock speed, and the number of streaming multiprocessors multiplied by the number of fragments per clock that they can output multiplied by the base clock rate.
^ Texture fillrate is calculated as the number of texture mapping units (TMUs) multiplied by the base (or boost) core clock speed.
^ Shading cores (ALU): texture mapping units (TMU): render output units (ROP): ray tracing units (tensor cores (XMX): execution units: render slices)
^Texture fillrate is calculated as the number of texture mapping units (TMUs) multiplied by the base (or boost) core clock speed.
^ Boost values (if available) are stated below the base value in italic.
^Pixel fillrate is calculated as the lowest of three numbers: number of ROPs multiplied by the base core clock speed, number of rasterizers multiplied by the number of fragments they can generate per rasterizer multiplied by the base core clock speed, and the number of streaming multiprocessors multiplied by the number of fragments per clock that they can output multiplied by the base clock rate.
^ Shading cores (ALU): texture mapping units (TMU): render output units (ROP): ray tracing units (tensor cores (XMX): execution Units: render slices)
^ Boost values (if available) are stated below the base value in italic.
^ Pixel fillrate is calculated as the lowest of three numbers: number of ROPs multiplied by the base core clock speed, number of rasterizers multiplied by the number of fragments they can generate per rasterizer multiplied by the base core clock speed, and the number of streaming multiprocessors multiplied by the number of fragments per clock that they can output multiplied by the base clock rate.
^ Texture fillrate is calculated as the number of texture mapping units (TMUs) multiplied by the base (or boost) core clock speed.
^"Intel® Data Center GPU Max Series Product Brief"(PDF). Intel. 2023-08-15. Retrieved 2023-11-03. Based on the Xe HPC architecture that uses both EMIB 2.5D and Foveros packaging technologies to combine 47 active tiles onto a single GPU, fabricated on five different process nodes, Intel Max Series GPUs enable greater flexibility and modularity in the construction of the SOC.
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